Metal gate structure

ABSTRACT

The present disclosure provides a semiconductor structure, including a substrate, a metal gate, a dielectric layer, and an etch stop layer. The metal gate is positioned on the substrate and possesses a first surface. The dielectric layer surrounds the metal gate and possesses a second surface. The etch stop layer is in contact with both the first surface and the second surface. The first surface is higher than the second surface. The present disclosure also provides a method for manufacturing a semiconductor structure, including forming a dummy gate on a substrate; forming a second etch stop layer over the dummy gate; forming a dielectric layer over the dummy gate; replacing the dummy gate with a metal gate; etching back the dielectric layer to form a second surface of the dielectric layer lower than a first surface of the metal gate; and forming a first etch stop layer over the metal gate and the dielectric layer.

BACKGROUND

In today's rapidly advancing world of semiconductor manufacturing,integration levels are increasing, device features are becoming smallerand greater demands are being made for improved device performance. AsCMOS, complementary metal oxide semiconductor, devices are scaled tosmaller sizes for future technologies, new materials and concepts arenecessary to meet the advanced performance requirements.

CMOS technology includes NMOS (N-type metal oxide semiconductor) andPMOS (P-type metal oxide semiconductor) devices formed on the samesubstrate and in the same die. A critical aspect of high performance inNMOS and PMOS and various other devices is device speed. For devices tooperate at high speeds, it is necessary to have a very low resistance,including a very low contact resistance between metal interconnectstructures and the NMOS and PMOS transistors. Contact is made to thegate electrodes of the respective transistors as well as to both thesource and drain regions of the associated transistors. One approach toprovide contacts to both the source and drain regions is to formtrenches penetrating through the dielectric layers above the source anddrain regions and then fill the trenches with conductive materials.

During the scaling trend, various materials have been used for the gateelectrode and gate dielectric for CMOS devices. One approach is tofabricate these devices with a metal material for the gate electrode anda high-k dielectric for the gate dielectric. However, high-k metal gate(HKMG) devices often require additional layers in the gate structure.For example, work function layers may be used to tune the work functionvalues of the metal gates. Additionally, barrier (or capping) layers mayassist in the HKMG manufacturing process. Although the combination ofsource/drain contact and HKMG formation have been satisfactory for theirintended purpose, they have not been satisfactory in all respects.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is a cross sectional view of a metal gate structure without asource/drain contact, in accordance with some embodiments of the presentdisclosure;

FIG. 2 is a top view dissecting from line AA of the metal gate structureshown in FIG. 1, in accordance with some embodiments of the presentdisclosure;

FIG. 3 is a top view dissecting from line BB of the metal gate structureshown in FIG. 1, in accordance with some embodiments of the presentdisclosure;

FIG. 4 is a cross sectional view of a metal gate structure with asource/drain contact, in accordance with some embodiments of the presentdisclosure;

FIG. 5 to FIG. 10 are cross sectional views showing operations of amethod for manufacturing a metal gate of a semiconductor structure, inaccordance with some embodiments of the present disclosure;

FIG. 11 to FIG. 13 are cross sectional views showing operations of amethod for manufacturing an etch stop layer of a semiconductorstructure, in accordance with some embodiments of the presentdisclosure; and

FIG. 14 to FIG. 15 are cross sectional views showing operations of amethod for manufacturing a source/drain contact of a semiconductorstructure, in accordance with some embodiments of the presentdisclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

As the size of the device scales down, several manufacturing operationsexploited in the larger scale device show significant problems in thereduced scale. For example, the formation of a source/drain contact in ametal gate transistor having a channel length of about 20 nm or lessshows an emptied metal gate in accordance to the custom operations. Theformation of a source/drain region contact in a metal gate transistorusually includes the following steps: (i) forming a bottom etch stoplayer of a metal gate; (ii) forming a interlayer dielectric (ILD) overthe bottom etch stop layer; (iii) planarizing the ILD and the bottometch stop layer until a top surface of the metal gate is exposed; (iv)forming a top etch stop layer over the top surface of the metal gate;(v) forming source/drain region contact hole by introducing etchantsthat removes the ILD and both the bottom and the top etch stop layer.

According to the operation described above, an interface situatedbetween the ILD and the top etch stop layer affects as a leakage pathallowing the etchants to penetrate through until reaching the metallayers of the metal gate while forming the source/drain contact hole.When the suitable etchants used to form the source/drain contact holehas a finite etch rate to the metal layers of the metal gate, theleakage path provides a channel for the metal layers to be etched andemptied. For example, a filling metal layer (e.g. a tungsten layer) ofthe metal gate is completely removed using the operation describedabove. For another example, a filling metal layer (e.g. a tungstenlayer), a work function metal layer (e.g. an aluminum-containing nitridelayer), a barrier layer (e.g. a nitride layer), and a capping layer(e.g. a nitride layer) are all removed and emptied in accordance to theoperation described above. Either the partial or the complete removal ofthe metal gate lowers the yield and/or reliability of the device, andthus the removal/emptying phenomena of the metal gate after source/draincontact hole formation shall be prevented.

Given the above problems faced by the sub-20 nm metal gate transistorstructure, a semiconductor structure with a cutoff leakage path isprovided in the present disclosure. The interface between the etch stoplayer and the ILD is tailored to end at a predetermined distance awayfrom the metal layers of the metal gate, and hence the leakage path forcontact hole etchants is blocked from the metal gate. A manufacturingmethod of the semiconductor structure with a cutoff leakage path is alsoprovided in the present disclosure. In some embodiments, 70% of themetal gates are retained after the contact hole formation by utilizingthe operations disclosed in the present disclosure.

FIG. 1 shows a cross sectional view of a metal gate transistor structure10 without a source/drain contact plug, in accordance to someembodiments of the present disclosure. The metal gate transistorstructure 10 includes a substrate 100, a metal gate 103 positioned onthe substrate, a dielectric layer 105 surrounding the metal gate 103,and an etch stop layer 107A, 107B over the metal gate 103 and thedielectric layer 105. In some embodiments, the substrate 100 is asemiconductor substrate including an elementary semiconductor such assilicon or germanium in crystal, polycrystalline, or an amorphousstructure; a compound semiconductor including silicon carbide, galliumarsenic, gallium phosphide, indium phosphide, indium arsenide, and/orindium antimonide; an alloy semiconductor including SiGe, GaAsP, AlinAs,AlGaAs, GaInAs, GaInP, and/or GaInAsP; any other suitable material;and/or combinations thereof. In one embodiment, the alloy semiconductorsubstrate may have a gradient SiGe feature in which the Si and Gecomposition change from one ratio at one location to another ratio atanother location of the gradient SiGe feature. In another embodiment,the alloy SiGe is formed over a silicon substrate. In anotherembodiment, a SiGe substrate is strained. Furthermore, the substrate 100may be a semiconductor on insulator, such as a silicon on insulator(SOI), or a thin film transistor (TFT). In some examples, the substrate100 may include a doped epi layer or a buried layer. In other examples,the substrate 100 may have a multilayer compound semiconductorstructure. In some embodiments, the substrate 100 may comprise anon-semiconductor material, such as glass.

The substrate 100 may include various doping configurations depending ondesign requirements as known in the art. In some embodiments, thesubstrate 100 may include doped regions. The doped regions may be dopedwith p-type or n-type dopants. For example, the doped regions may bedoped with p-type dopants, such as boron or BF₂; n-type dopants, such asphosphorus or arsenic; and/or combinations thereof. The doped regionsmay be formed directly on the semiconductor substrate, in a P-wellstructure, in a N-well structure, in a dual-well structure, or using araised structure. The substrate 100 may further include various activeregions, such as regions configured for an N-typemetal-oxide-semiconductor transistor device (referred to as an NMOS) andregions configured for a P-type metal-oxide-semiconductor transistordevice (referred to as a PMOS). It is understood that the metal gatetransistor structure 10 may be formed by complementarymetal-oxide-semiconductor (CMOS) technology processing, and thus someprocesses are not described in detail herein. In some embodiments, themetal gate transistor structure 10 may include epitaxial growths in thesource and drain regions on each side of the gate structure and forminga raised source and drain regions 101, the epitaxial growths impartingtensile strain or compressive strain to the channel region.

At least one isolation region 102 may be formed on the substrate 100 toisolate various regions, for example, to isolate NMOS and PMOStransistor device regions as shown in FIG. 4. The isolation region 102may utilize isolation technology, such as local oxidation of silicon(LOCOS) or shallow trench isolation (STI), to define and electricallyisolate the various regions. In the present embodiment, the isolationregion 102 includes an STI. The isolation region 102 may comprisesilicon oxide, silicon nitride, silicon oxynitride, fluoride-dopedsilicate glass (FSG), a low-K dielectric material, other suitablematerials, and/or combinations thereof.

Referring to FIG. 1, the metal gate 103 may include a gate spacer 1031,which are positioned on each side of the metal gate 103, composed of,for example, a nitride material (e.g., silicon nitride). The gatespacers 1031 may include a dielectric material such as silicon nitride,silicon oxide, silicon carbide, silicon oxynitride, other suitablematerials, and/or combinations thereof. The gate spacers 1031 may beused to offset the source and drain regions 101 (also referred to asheavily doped source/drain regions), as opposed to the lightly dopedsource/drain regions 101′. In some embodiments, a sidewall of the metalgate described in the present disclosure refers to the outer surface ofthe gate spacer 1031.

In FIG. 1, the etch stop layer 107A, 107B may include silicon nitride,silicon oxynitride, amorphous carbon material, silicon carbide and/orother suitable materials. The etch stop layer 107A, 107B composition maybe selected based upon etching selectivity to one or more additionalfeatures of the metal gate transistor structure 10. In the presentembodiment, the etch stop layer 107B is a middle contact etch stop layer(MCESL) composed at least of silicon nitride, and the etch stop layer107A is a bottom contact etch stop layer (BCESL) composed of the same ofdifferent dielectric materials as those in the MCESL. The etch stoplayer 107A, 107B may possess any suitable thickness, for example, fromabout 30 Å to about 150 Å.

In FIG. 1, the dielectric layer 105 may include materials such assilicon oxide, silicon nitride, silicon oxynitride, spin-on glass (SOG),fluorinated silica glass (FSG), carbon doped silicon oxide (e.g.,SiCOH), Black Diamond® (Applied Materials of Santa Clara, Calif.),Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB(bis-benzocyclobutenes), Flare, SiLK (Dow Chemical, Midland, Mich.),polyimide, non-porous materials, porous materials, and/or combinationsthereof. In some embodiments, the dielectric layer 105 may include ahigh density plasma (HDP) dielectric material (e.g., HDP oxide) and/or ahigh aspect ratio process (HARP) dielectric material (e.g., HARP oxide).The dielectric layer 105 may possess any suitable thickness, such asfrom about 3000 Å to about 5000 Å. It is understood that the dielectriclayer 105 may comprise one or more dielectric materials and/or one ormore dielectric layers.

As shown in FIG. 1, the metal gate 103 refers to the gate spacer 1031and several metal layers (1032, 1033, 1034, 1035, 1036). In someembodiments, the several metal gate layers include an interlayer or ahigh k dielectric layer 1032, a high k dielectric capping layer 1033, abarrier or an etch stop layer 1034, a work function metal layer 1035,and a metal filling layer 1036. People having ordinary skill in the artshall understand that various sequence or additional/reduced metal layermay be constructed and thus is not exceeding the scope of the presentdisclosure.

Referring to FIG. 1, the metal gate 103 possesses a first surface 103A,in some embodiments, as a top surface of the metal gate 103. Thedielectric layer 105 possesses a second surface 105A, in someembodiments, as a top surface of the dielectric layer 105. The firstsurface 103A can be further defined as an interface between the topsurface of the metal gate and the etch stop layer 107B, and the secondsurface 105A can be further defined as an interface between thedielectric layer 105 and the etch stop layer 107B. In FIG. 1, the etchstop layer 107B is in contact with the first surface 103A and the secondsurface 105A at different level of height, respectively. In other words,for example, the first surface 103A is higher than the second surface105A by a predetermined distance H1.

In some embodiments, the predetermined distance H1 between the firstsurface 103A and the second surface 105A is in a range of from about 30Å to about 80 Å. For example, the first surface 103A of the metal gate103 is 50 Å higher than the second surface 105A of the dielectric layer105. In some embodiments, the etch stop layer 107A, 107B includes twoportions: an upper portion 107B and a lower portion 107A. The upperportion 107B is positioned over the metal gate 103 and the dielectriclayer 105, whereas the lower portion 107A is in contact with a thirdsurface 105B of the dielectric layer. The third surface 105B is furtherdescribed later in the present disclosure. As shown in FIG. 1, the upperportion 107B and the lower portion 107A of the etch stop layer from acontinuous region where the upper portion 107B is physically inconnection to the lower portion 107A at least at the position close tothe sidewall of the metal gate 103.

In some embodiments, the lower portion 107A surrounds a third surface105B of the dielectric layer 105. The third surface 105B of thedielectric layer 105 refers to the contour of the dielectric layer 105other than the second surface 105A. In other words, the third surface105B may include a horizontal part located at a bottom of the dielectriclayer 105 and a vertically oblique part located at a sidewall of thedielectric layer 105. As discussed previously, the lower portion 107Acan be a BCESL which is conformal to the morphology of the metal gate103, and thus the lower portion 107A is surrounding the third surface105B of the dielectric layer 105.

To further clarify the metal gate transistor structure 10 in FIG. 1, atop perspective viewing from the plane sectioning along line AA and lineBB of FIG. 1 are shown in FIG. 2 and FIG. 3, respectively. In FIG. 1 andFIG. 2, line AA is crossing the first surface 103A of the metal gate 103and laterally extending to the upper portion 107B of the etch stoplayer. In FIG. 1 and FIG. 3, line BB is crossing the second surface 105Aand laterally extending to the metal gate 103. In FIG. 2, the metal gate103 includes the gate spacer 1031, the interlayer or a high k dielectriclayer 1032, the high k dielectric capping layer 1033, the barrier or theetch stop layer 1034, the work function metal layer 1035, and the metalfilling layer 1036. The upper portion 107B of the etch stop layer is atthe two sides of the metal gate 103. In FIG. 3, labels having identicalnumerals are referred to the same elements as those in FIG. 1 and FIG.2, and are not repeated here for simplicity. Compared to FIG. 2, the topperspective view in FIG. 3 further includes the dielectric layer 105sandwiching the metal gate 103 and the lower portion 107A of the etchstop layer.

As shown in FIG. 2, the upper portion 107B of the etch stop layer is incontact with the sidewall of the metal gate 103. In some embodiments,the sidewall of the metal gate 103 can be the gate spacer 1031.Similarly, as shown in FIG. 3, the lower portion 107A of the etch stoplayer is in contact with the sidewall of the metal gate 103. Because alower portion of the metal gate 103 is surrounded both by the etch stoplayer 107A and the dielectric layer 105, the lower portion 107A of theetch stop layer has a defined width H2 which can be measured from theedge of the second surface 105A to the sidewall of the metal gate 103.

As discussed previously in the present disclosure, the etch stop layer107A, 107B and the dielectric layer 105 may be composed of differentmaterials possessing different etch rates. For example, under a dry etchoperation including fluorine-containing gases (e.g., CF₄, SF₆, CH₂F₂,CHF₃, and/or C₂F₆), the etch rate of the etch stop layer 107A, 107B(e.g. nitride-based layer) is slower than the etch rate of thedielectric layer 105 (e.g. oxide-based layer). In some embodiments, theselectivity (etch rate ratio of the dielectric layer 105 and the etchstop layer 107A, 107B) under a dry etch operation includingfluorine-containing gases is around 4. On the other hand, under a wetetch operation including diluted hydrofluoric acid (HF) dipping process,the selectivity between the dielectric layer 105 and the etch stop layer107A, 107B is in a range of from about 5 to about 10.

FIG. 4 is a cross sectional view of a metal gate structure 20 with asource/drain contact, in accordance with some embodiments of the presentdisclosure. The metal gate structure 20 includes a substrate 100, anNMOS metal gate 103, and a PMOS metal gate 103′ on the substrate 100. Insome embodiments, the NMOS structure may include epitaxially regrownsource and drain regions 101 imparting a tensile strain to a channelregion; the PMOS structure may include epitaxially regrown source anddrain regions 106 imparting a compressive strain to a channel region. Insome embodiments, the metal gate structure 20 is constructed in aFinFET, and thereby the substrate 100 is a semiconductor fin partiallyembedded in an insulating layer (not shown).

Referring to FIG. 4, the NMOS metal gate 103 includes a first portion1037 and a second portion 1039. The first portion 1037 directs to anupper portion of the metal gate 103, surrounded by the upper portion107B of the etch stop layer 107A, 107B or a first etch stop layer. Thesecond portion 1039 directs to a lower portion of the metal gate 103,surrounded by the lower portion 107A (or a second etch stop layerpreviously discussed in the present disclosure) and a dielectric layer105. Also can be seen from FIG. 4, an interface 1038 between the firstetch stop layer 107B and the dielectric layer 105 is terminated at apredetermined distance H2 from the sidewall of the metal gate 103, andthus said interface 1038 is not in contact with the metal gate 103. Insome embodiments, the predetermined distance H2 is in a range of fromabout 30 Å to about 80 Å.

In FIG. 4, the intersection of the first etch stop layer 107B, thesecond etch stop layer 107A, and the dielectric layer 105 form a triplepoint T. In some embodiments, the triple point T is lower than the firstsurface 103A of the metal gate 103. In other embodiments, the triplepoint T is laterally a distance H2 away from the sidewall of the metalgate 103. The NMOS metal gate 103 and its surrounding environment can beapplied to the PMOS metal gate 103′, and thus the detailed descriptionof the PMOS metal gate 103′ shown in FIG. 4 is omitted for simplicity.

Still referring to FIG. 4, the etch stop layer 107A, 107B and thedielectric layer 105 may be composed of different materials possessingdifferent etch rates. For example, under a dry etch operation includingfluorine-containing gases (e.g., CF₄, SF₆, CH₂F₂, CHF₃, and/or C₂F₆),the etch rate of the etch stop layer 107A, 107B (e.g. nitride-basedlayer) is at least 3 times slower than the etch rate of the dielectriclayer 105 (e.g. oxide-based layer). In some embodiments, the selectivity(etch rate ratio of the dielectric layer 105 and the etch stop layer107A, 107B) under a dry etch operation including fluorine-containinggases is around 4. On the other hand, under a wet etch operationincluding diluted hydrofluoric acid (HF) dipping process, theselectivity between the dielectric layer 105 and the etch stop layer107A, 107B is in a range of from about 5 to about 10.

Still referring to FIG. 4, the source and drain contacts 111electrically couple the source and drain regions 101, 106 of the metalgate structure 20 to metallization layers (not shown) and othersemiconductor devices (not shown). The source and drain contacts 111 arecomposed of a contact hole filled with conductive materials. The contacthole at least penetrates through an oxide layer 109, the first etch stoplayer 107B, the dielectric layer 105, and the second etch stop layer107A, engaging respective silicide layers (not shown) over the sourceand drain regions 101, 106. In some embodiments, the conductivematerials forming the contacts 111 include aluminum, copper, tungsten,titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide,cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, other suitablematerials, and/or combinations thereof.

The present disclosure also provides a method for manufacturing asemiconductor structure described herein. In some embodiments, the crosssectional views in FIG. 5 to FIG. 6 demonstrate forming a dummy gate 104on a substrate; the cross sectional view in FIG. 7 demonstrates forminga first etch stop layer 107A over the dummy gate 104 and forming adielectric layer 105 over the dummy gate 104; the cross sectional viewsin FIG. 8 to FIG. 10 demonstrate replacing the dummy gate 104 with ametal gate 103; the cross sectional view in FIG. 11 demonstrates etchingback the dielectric layer 105 to form a second surface 105A of thedielectric layer lower than a first surface 103A of the metal gate; thecross sectional views from FIG. 12 to FIG. 13 demonstrate forming asecond etch stop layer 107B over the metal gate 103 and the dielectriclayer 105.

In FIG. 5, a dummy gate layer 104′ is deposited on a substrate 100 andsubsequently photolithography patterned to form a dummy gate 104 in FIG.6. An optional interfacial layer 100′ may be deposited between thesubstrate and the dummy gate layer 104′ and subsequently patterned. Thedeposition operation may include chemical vapor deposition (CVD),physical vapor deposition (PVD), atomic layer deposition (ALD), highdensity plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasmaCVD (RPCVD), plasma enhanced CVD (PECVD), epitaxial growth methods(e.g., selective epitaxy growth), sputtering, plating, spin-on coating,other suitable methods, and/or combinations thereof. Thephotolithography patterning operation may include photoresist coating(e.g., spin-on coating), soft baking, mask aligning, exposure,post-exposure baking, developing the photoresist, rinsing, drying (e.g.,hard baking), other suitable processes, and/or combinations thereof. Thephotolithography exposing process may also be implemented or replaced byother proper methods such as maskless photolithography, electron-beamwriting, ion-beam writing, and/or molecular imprint. The etchingprocesses may include dry etching, wet etching, and/or other etchingmethods (e.g., reactive ion etching). The etching process may also beeither purely chemical (plasma etching), purely physical (ion milling),and/or combinations thereof.

In FIG. 7, a gate spacer 1031 is formed at the sidewall of the dummygate 104, and a lower portion 107A of the etch stop layer (or a secondetch stop layer previously referred to in the present disclosure) isconformally deposited over the dummy gate 104. In some embodiments, thegate spacer 1031 and the bottom etch stop layer 107A are deposited byCVD operation suitable for nitride materials. A dielectric layer 105 isthen blanket formed over the dummy gate 104 and the conformal layers. Asshown in FIG. 7, in some embodiments, the source/drain regions 101 canbe epitaxially regrown by, for example, a stress memorization technique(SMT), or other suitable regrowth operation prior to the formation ofthe bottom etch stop layer 107A.

FIG. 8 to FIG. 10 show a removal of the dummy gate 104 and a replacementby a metal gate 103. A top planarization operation may be conducted onthe intermediate semiconductor structure of FIG. 7 to remove thedielectric layer 105, the bottom etch stop layer 107A, and the gatespacer 1031, until the exposure of a top surface of the dummy gate 104.In FIG. 8, the dummy gate 104 is removed to form a recess 1040 by anysuitable etching operations. In some embodiments, a high k dielectriclayer 1032, a high k dielectric capping layer 1033, a barrier or an etchstop layer 1034, a work function layer 1035, and a metal filling layer1036 are sequentially formed in the recess 1040.

Among the multiple layers in the metal gate 103, the work function layer1035 is tuned to have a proper work function and comprises any suitablematerial. For example, if a P-type work function metal (P-metal) for aPMOS device is desired, TiN, WN, or W may be used. On the other hand, ifan N-type work function metal (N-metal) for NMOS devices is desired,TiAl, TiAlN, or TaCN, may be used. In some embodiments, the workfunction layer 1035 may include doped-conducting metal oxide materials.The metal filling layer 1036 includes any suitable conductive materialpreviously discussed herein. Further, the metal filling layer 1036 maybe doped polycrystalline silicon with the same or different doping. Insome embodiment, the metal filling layer 1036 includes aluminum. It isunderstood that additional layers may be formed above and/or below thework function layer 1035 and/or metal filling layer 1036, includingliner layers, interface layers, seed layers, adhesion layers, barrierlayers, etc. It is further understood that the work function layer 1035and metal filling layer 1036 may include one or more materials and/orone or more layers.

In FIG. 10, a removal operation is performed to remove the metal gatelayers (1032, 1033, 1034, 1035, 1036) positioned over the dielectriclayer 105 until the exposure of a top surface 105′ of the dielectriclayer 105. In some embodiments, the top surface 105′ is coplanar to thefirst surface 103A of the metal gate 103. In some embodiments, theremoval operation includes a chemical mechanical polishing (CMP)operation and/or other suitable planarization operations.

Following FIG. 10, the top surface 105′ of the dielectric layer 105 isfurther etched back to form a depressed surface 105A (or a secondsurface previously discussed in the present disclosure), for example,about 30 Å to about 80 Å of the dielectric layer 105 is removed and thesecond surface 105A is lower than the first surface 103A by apredetermined distance H1. In some embodiments, the predetermineddistance H1 shall be large enough to allow the subsequently formed firstetch stop layer 107B to contact with the sidewall of the metal gate 103,but small enough to prevent the resistivity of the semiconductorstructure from increasing.

The etching back operation may include one or more dry etchingprocesses, wet etching processes, other suitable processes (e.g.,reactive ion etching), and/or combinations thereof. In some embodiments,any etching operation demonstrating a sufficient higher etch rate on thedielectric layer 105 than on the metal gate 103 and the second etch stoplayer 107A is within the contemplated scope of the present disclosure.In some embodiments, etching operations showing an etch rate of about0:1:4 among the metal gate 103, the second etch stop layer 107A, and thedielectric layer 105 can be used in the present disclosure.

In some embodiments, the etching back operation may be either purelychemical (plasma etching), purely physical (ion milling), and/orcombinations thereof. For example, a dry etching process may beimplemented in an etching chamber using process parameters including aradio frequency (RF) source power, a bias power, a pressure, a flowrate, a wafer temperature, other suitable process parameters, and/orcombinations thereof. The dry etching process may implement anoxygen-containing gas, fluorine-containing gas (e.g., CF₄, SF₆, CH₂F₂,CHF₃, and/or C₂F₆), chlorine-containing gas (e.g., Cl₂, CHCl₃, CCl₄,and/or BCl₃), bromine-containing gas (e.g., HBr and/or CHBR₃),iodine-containing gas, other suitable gases and/or plasmas, and/orcombinations thereof. In some embodiments, the dry etching processutilizes an O₂ plasma treatment and/or an O₂/N₂ plasma treatment.Further, the dry etching process may be performed for any suitable time.A wet etching process may utilize a hydrofluoric acid (HF) solution fora HF dipping process. The HF solution may have any suitableconcentration (e.g., 1:100). In some embodiments, a wet etching processmay apply a diluted hydrofluoric acid to the intermediate semiconductorstructure.

Following FIG. 11, an upper etch stop layer 107B (or a first etch stoplayer previously discussed in the present disclosure) is formed over themetal gate 103 and the dielectric layer 105 by a nitride depositionoperation as shown in FIG. 12. In some embodiments, the first etch stoplayer 107B is deposited using the same operation as the second etch stoplayer 107A. In other embodiments, the first etch stop layer 107B isdeposited using different operations as the second etch stop layer 107A.By using the operations described in the present disclosure, theinterface 1038 between the first etch stop layer 107B and the dielectriclayer 105 is below the first surface 103A of the metal gate 103, as wellas the first etch stop layer 107B and the second etch stop layer 107Aare in connection to each other in proximity to the sidewall of themetal gate 103. In other words, the portion connecting the first etchstop layer 107B and the second etch stop layer 107A terminates theinterface 1038, and prevents the triple point T from contacting thesidewall of the metal gate 103. In FIG. 13, a planarization operation isconducted on the first etch stop layer 107B to form a leveled surface107C, and then subsequently an oxide layer 109 is formed over theleveled surface 107C.

FIG. 14 to FIG. 15 show a contact formation operation according to someembodiments of the present disclosure. In FIG. 14, the oxide layer 107C,the first etch stop layer 107B, the dielectric layer 105, and the secondetch stop layer 107A is removed to form a contact hole 111′ via aphotolithography operation. In some embodiments, a bottom of the contacthole is further undergone a silicidation (or self-aligned silicidation)operation. Silicide material 140 is formed on the surface of thesource/drain region. Contacts 111 in FIG. 15 provide electricalconnection to the S/D regions 101 (via silicide regions). The contacts111 may be formed by filling the contact holes 111′ with conductivematerials. The conductive materials may include aluminum, copper,tungsten, titanium, tantalum, titanium nitride, tantalum nitride,nickel, cobalt, TaC, TaSiN, TaCN, TiAl, TiAlN, other suitable materials,and/or combinations thereof.

FIG. 5 to FIG. 15 of the present disclosure do not limit thesemiconductor structure to a planar transistor, but are intended toencompass the non-planar transistor such as a FinFET. The crosssectional views for the operations provided in FIG. 5 to FIG. 15 can beinterpreted as a metal gate FinFET structure with a semiconductor fin100 instead of a substrate 100 previously referred to in the presentdisclosure.

Some embodiments of the present disclosure provide a semiconductorstructure, including a substrate, a metal gate, a dielectric layer, andan etch stop layer. The metal gate is positioned on the substrate andpossesses a first surface. The dielectric layer surrounds the metal gateand possesses a second surface. The etch stop layer is over the metalgate and the dielectric layer, and the etch stop layer is in contactwith both the first surface and the second surface. The first surface iselevated or higher than the second surface.

In some embodiments of the present disclosure, the first surface ishigher than the second surface by a range of from about 30 Å to about 80Å.

In some embodiments of the present disclosure, the etch stop layersurrounds a third surface of the dielectric layer.

In some embodiments of the present disclosure, the etch stop layerincludes an upper portion and a lower portion. The upper portion and thelower portion forms a continuous etch stop layer.

In some embodiments of the present disclosure, the lower portion of theetch stop layer is in contact with a sidewall of the metal gate.

In some embodiments of the present disclosure, the upper portion of theetch stop layer is in contact with a sidewall of the metal gate.

In some embodiments of the present disclosure, the etch stop layerincludes materials with an etch rate lower than an etch rate of thedielectric layer under a fluorine-containing etch.

Some embodiments of the present disclosure provide a semiconductorstructure. The semiconductor includes a substrate and a gate positionedon the substrate. The gate further includes a first portion and a secondportion. The first portion of the gate is surrounded by a first etchstop layer, and the second portion of the gate is surrounded by a secondetch stop layer and a dielectric layer. An interface between the firstetch stop layer and the dielectric layer is not in contact with thegate.

In some embodiments of the present disclosure, the first etch stoplayer, the second etch stop layer and the dielectric layer form a triplepoint away from the gate.

In some embodiments of the present disclosure, a separation between thetriple point and a sidewall of the gate is in a range of from about 30 Åto about 80 Å.

In some embodiments of the present disclosure, the first etch stop layerand the second etch stop layer includes materials with an etch rate atleast three times slower than an etch rate of the dielectric layer undera fluorine-containing etch.

In some embodiments of the present disclosure, the semiconductorstructure further includes a contact connecting a source or a drainregion to an external conductive path. The contact penetrates the firstetch stop layer, the dielectric layer, and the second etch stop layer toreach the source or the drain region.

In some embodiments of the present disclosure, the gate is an NMOS metalgate or a PMOS metal gate.

Some embodiments of the present disclosure provide a method formanufacturing a semiconductor structure. The method includes forming adummy gate on a substrate; forming a second etch stop layer over thedummy gate; forming a dielectric layer over the dummy gate; replacingthe dummy gate with a metal gate; etching back the dielectric layer toexpose a portion of the sidewall of the meta gate; and forming a firstetch stop layer over the metal gate and the dielectric layer.

In some embodiments of the present disclosure, the etching back thedielectric layer includes performing a dry etch operation etching backthe dielectric layer by a thickness of from about 30 Å to about 80 Å.

In some embodiments of the present disclosure, the etching back thedielectric layer includes performing a dry etch with an etch rate ratioof about 0:1:4 among the metal gate, the first etch stop layer; and thedielectric layer.

In some embodiments of the present disclosure, the etching back thedielectric layer includes performing a dry etch with fluorine-containingmaterials.

In some embodiments of the present disclosure, the forming a first etchstop layer over the metal gate and the dielectric layer includesdepositing the first etch stop layer and planarizing the deposited firstetch stop layer.

In some embodiments of the present disclosure, the replacing the dummygate with a metal gate includes removing the dummy gate, forming themetal gate, and removing the metal gate to expose a top surface of thedielectric layer.

In some embodiments of the present disclosure, the method formanufacturing the semiconductor structure further includes forming asource or a drain contact that is penetrating the second etch stoplayer, the dielectric layer, and the first etch stop layer to reach thesource or the drain region.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A semiconductor structure, comprising: asubstrate; a metal gate with a first surface, positioned on thesubstrate; and a dielectric layer with a second surface, surrounding themetal gate; and an etch stop layer at least over the metal gate and thedielectric layer, in contact with the first surface and the secondsurface, wherein the first surface is higher than the second surface. 2.The semiconductor structure of claim 1, wherein the first surface ishigher than the second surface by a range of from about 30 Å to about 80Å.
 3. The semiconductor structure of claim 1, wherein the etch stoplayer surrounds a third surface of the dielectric layer.
 4. Thesemiconductor structure of claim 3, wherein the etch stop layercomprises an upper portion and a lower portion, the upper portion andthe lower portion constituting a continuous etch stop layer.
 5. Thesemiconductor structure of claim 4, wherein the lower portion of theetch stop layer is in contact with a sidewall of the metal gate.
 6. Thesemiconductor structure of claim 4, wherein the upper portion of theetch stop layer is in contact with a sidewall of the metal gate.
 7. Thesemiconductor structure of claim 3, wherein the etch stop layercomprises materials with an etch rate lower than an etch rate of thedielectric layer under a fluorine-containing etch.
 8. The semiconductorstructure of claim 3, wherein the second surface, the third surface, andthe dielectric layer form a triple point away from the metal gate. 9.The semiconductor structure of claim 8, wherein a separation between thetriple point and a sidewall of the metal gate is in a range of fromabout 30 Å to about 80 Å.
 10. The semiconductor structure of claim 3,wherein the third surface comprises a horizontal part at a bottom of thedielectric layer and a vertically oblique part at a sidewall of thedielectric layer.
 11. The semiconductor structure of claim 1, whereinthe metal gate is positioned on a fin of a FinFET.
 12. A semiconductorstructure, comprising: a substrate; and a gate on the substrate,comprising: a first portion surrounded by a first etch stop layer; and asecond portion surrounded by a second etch stop layer and a dielectriclayer, wherein an interface between the first etch stop layer and thedielectric layer is not in contact with the gate.
 13. The semiconductorstructure of claim 12, wherein the first etch stop layer, the secondetch stop layer and the dielectric layer form a triple point away fromthe gate.
 14. The semiconductor structure of claim 13, wherein aseparation between the triple point and a sidewall of the gate is in arange of from about 30 Å to about 80 Å.
 15. The semiconductor structureof claim 12, wherein the first etch stop layer and the second etch stoplayer comprise materials with an etch rate at least three times slowerthan an etch rate of the dielectric layer under a fluorine-containingetch.
 16. The semiconductor structure of claim 12, further comprising acontact connecting a source or a drain region to an external conductivepath, and the contact penetrating the first etch stop layer, thedielectric layer, and the second etch stop layer.
 17. The semiconductorstructure of claim 12, wherein the gate is an NMOS metal gate or a PMOSmetal gate.
 18. The semiconductor structure of claim 12, furthercomprising: a first surface between the first portion of the gate andthe first etch stop layer; and a second surface between the dielectriclayer and the first etch stop layer, wherein the first surface is higherthan the second surface.
 19. The semiconductor structure of claim 12,wherein the first etch stop layer comprises a horizontal part at abottom of the dielectric layer and the second etch stop layer comprisesa vertically oblique part at a sidewall of the dielectric layer.
 20. Thesemiconductor structure of claim 12, wherein the gate is positioned on afin of a FinFET.